The feature size of integrated circuit semiconductor devices has decreased steadily and as a result the performance of the interconnections between different portions of the device has become an increasingly significant factor in the performance of the device as a whole. Furthermore, the increasing complexity and reduction in size of the devices has increased the need for multi-layer interconnects.
Such interconnects may be manufactured using the so-called “damascene” process, in which a dielectric layer is formed and then etched away leaving a pattern of trenches defining the paths of the desired interconnections. Interconnect metal is then deposited to fill the trenches. This leaves an uneven surface formed by excess metal. A chemical-mechanical polishing (CMP) step is then used to planarize the structure, removing the excess metal from the surface to provide a flat surface suitable for further processing.
Typically, a multi-layer structure is built up from alternating trench layers and via layers. The trench layers include the horizontal interconnects and the via layers provide the vertical connections between the different levels of the multiple interconnect layers and to the underlying semiconductor device.
An important performance characteristic for interconnect structures is minimisation of transmission delays. Such delays are typically determined by the resistance and capacitance of the interconnect. For this reason, copper is increasingly preferred due to its relatively low resistance. Copper can be combined with insulating materials with low dielectric constants, known as low-k materials, to provide interconnects with good performance.